The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications.
As integrated circuits are designed to operate at increasingly higher frequencies, noisy, distorted, and/or inconsistent signals can cause devices such as output drivers to produce poor quality output. Preferably, an output driver may provide a clean, symmetric, well-shaped output waveform even if the input signals are noisy or of poor quality. However, a driver may receive an asymmetric, low quality differential signal with a substantial and/or inconsistent amplitude variation and/or a common mode component. In many cases, the quality of the differential input signal may degrade with increased operating frequency. An eye diagram, constructed by overlaying the output voltage waveforms for many clock cycles, may be used indicate the fidelity or quality of a signal put through an electronic buffer circuit. A high quality output waveform may have an eye diagram with a symmetric shape that approaches the shape of a square wave. Often, it is desirable to have an output waveform with a centered or controllable crossing point (the point where the rising and falling signals intersect). The output crossing point may be characterized by the crossing point voltage. For a differential output, each of the output waveforms has an associated crossing point voltage.
From the above, it is seen that techniques for improving output waveforms and regulating them are highly desirable.